application note 1 of 9 www.xicor.com october, 2000 an 113 serial memory interface: the bene?s of spi over i 2 c and wire by carlos martinez, october 1997 introduction in the dynamic semiconductor industry, conventions taken for gospel today are heresy tomorrow. in one of these classic battlegrounds, parallel busses, once undis- puted leader in system data transfer, face a serious challenge from new serial interfaces. recent introduc- tions and improved standards make the serial interface an attractive choice for both memory and peripheral control applications. in the peripheral arena, ieee1394, gigabit ethernet and universal serial bus (usb) are gaining favor in many systems over parallel busses such as pci, pccard, ide (disk drive), and isa/eisa. in the semiconductor memory world, code storage devices almost exclusively use the parallel bus. however, serial access data memories now ?d increasing acceptance as faster serial busses allow the designer to achieve the bene?s without the drawbacks. this application note examines serial memory interface trends and evaluates the three leading interface standards. memory density as parallel flash memories and eeproms increase in density, manufacturing lower density devices becomes increasingly less cost effective, so these densities tend to ?isappear? this provides opportunities for serial memories to increase in density to ll the gap?left by the discontinued parallel types. these serial memory devices prove ideal for many data storage applications. the emergence of serial memories serial memory devices have been around for more than 14 years. the early low density devices found their way into many applications and, because of their low cost, sold in high volumes. typical early uses included system con?uration or device identi?ation. these application generally required very little storage and had few inter- face speed constraints. in recent years, the use of serial nonvolatile memories has increased at a phenomenal rate into applications ranging from cellular telephones to lan systems to automobiles to industrial equipment. in many of these applications serial memories are begin- ning to displace parallel devices. figure 1. trends in memory density
2 of 9 an 113 application note www.xicor.com october, 2000 serial memories began to make inroads against parallel devices in response to two related market requirements. first was a rapid growth of portable products, as demon- strated by the proliferation of laptop computers, palmtop computers, pocket cellular phones, pagers, etc. porta- bility needs drove component vendors to ?d ways to reduce the size and power of their product. success in this area fueled more miniaturization and the trend points to continued miniaturization in the foreseeable future. as devices become more portable, there is a growing desire by consumers to customize the product that they use. products now are small enough that their owners carry them everywhere. they become part of the person s ?ife-style? when this happens, the product must adapt to the owners preferences and habits. this leads to an increasing need for user programmable customization. as devices get smaller, there are different interface media, since a keyboard is not always practical. this leads to voice or pen inputs. to optimize performance the system must adapt to the user or be capable of adjust- ment for more desirable response. customization in a system also includes personal phone numbers, individual schedules, stylized sounds or pictures. to personalize a product the user might include records of credit card numbers, access code lists, medical history, insurance information, etc. as personal- ization and customization becomes more common, there is a desire for more. this results in an ever growing need for more nonvolatile memory. one way to provide customized memory is to use a small piece of a large parallel flash device often seen in many products. the flash contains the operating code and can be updated in the ?ld. why not reserve a little of this space for data storage? the emerging consensus is that loss of some personalization data is manageable, but loss of program is catastrophic. allowing writes of personalization data to the same device that contains the program code increases the likelihood of catastrophic program failures in the ?ld with each new generation of product, engineers ?d new ways to reduce the physical size of the unit and to reduce it s power, while at the same time increasing the perfor- mance. to do this, the engineer uses device integration (through the use of asics and more highly integrated semiconductors), smaller packages, lower operating voltage, lower current and innovative packaging. serial memories are becoming increasingly important in managing programmability, board space and power. historical trends show serial memory power require- ments (figure 2) and memory density per square millimeter (figure 3) decreasing rapidly, with the trend continuing into the near future. because of their small size, low power characteristics and isolation from program memory areas, serial memories are key in providing new portable solutions. while serial memories seem to be the ideal solution, as densities increase they are troubled by one major limita- tion, speed.
3 of 9 an 113 application note www.xicor.com october, 2000 pe 2 spi power 1.8mw 1.8 w 15mw 750 w 400mw 250mw 100mw 75mw i 2 c 1988 1992 1995 year pe 2 spi 13.5mw 2.7 w 250mw 2.5mw 8mw 2.7 w i 2 c 1997 pe 2 82mw 500 w operating standby power i 2 c spi figure 2. memory power trends - with each new generation of devices power consumption is reduced. future devices will have zero standby power 75 70 65 60 55 50 45 40 35 30 25 20 15 10 8p-dip 8l-soic 14l-tssop 8l-tssop 8l-msop 20l-tssop 24l-tssop 1988 1992 1996 16l-soic 2000 4k 16k 32k 64k 128k 256k csp board space (mm 2 ) figure 3. memory density/package trends - as process technologies shrink device geometries, more memory can ? into smaller packages. the ultimate package is the chip itself. chip scale package technology, in development now, promises to radically reduce future package sizes.
4 of 9 an 113 application note www.xicor.com october, 2000 the importance of speed two new serial peripheral interface standards, the ieee1394 and usb, are examples of an increased push in the industry toward higher serial bus speeds. promo- tions for the 1gbit ieee1394 standard indicate that it may be the preferred choice over the parallel pci bus in the pc because of data throughput. at 1gb/s, the ieee1394 serial bus transfers 64-bits of data in less than 65ns. this is reportedly faster than current implementa- tions of the parallel pci bus, because of pci protocol overhead. designers predict the usb will replace the isa bus and both the pc parallel and serial bus in the pc for low speed peripherals. the usb handles up to 12mb/s. this is fast enough to handle audio i/o, tele- phone interfaces, keyboard and mouse control, printers and other standard pc peripherals. the usb is thought to have the inside track over other serial busses like access.bus (a derivative of i 2 c), mainly due to it s much higher speed. in serial memory applications speed becomes more important as the density increases. reading 64kbits, at 100khz takes over 600ms, while a 10mhz interface takes only 6ms. this can make a big difference in system performance, power consumption and user interaction. slow interface speeds impact system performance by adding overhead to the cpu. the need to wait for the next bit strains the ability of the processor to deal with real time activities or the demands of ever more complex software. this overhead can also affect the user of a product. the average person perceives a delay with response times in excess 200 to 300ms. faster response times do not interrupt thought processes and this gives the user a more solid feel about the product. slower response times re?ct poorly on the product, leading to dissatisfaction. interface speed, coupled with low standby current, can increase the battery life of a product. in many applica- tions, a product operates at full power only a fraction of the time. most often it is in some standby, low power state. executing an operation faster reduces the time a product is in full power mode, allowing it to remain in a standby state longer (figure 4). recent high speed serial memory product introductions from xicor have generated tremendous interest. this is an early indication that the simple serial memory inter- face speeds will track the serial peripheral bus trends. recent product introductions from xicor include 400khz 2-w ire and 5mhz spi devices. figure 5 shows a graphical representation of current and projected serial bus speeds. trends for the spi bus is based on projec- tions for expected host processor hardware capability and memory i/o design in the near future. interface options the earliest memory busses were the microwire bus and the i 2 c bus. the microwire bus began as an inter- processor communication port for the cops microcon- troller. the i 2 c (inter-integrated controller) bus began as a peripheral bus, meant to interface to many devices with a single set of two wires. spi is a synchronous peripheral interface that was created by motorola. this interface is a more recent introduction that is proliferating as high speed becomes more important and as more products exploit the interface.
5 of 9 an 113 application note www.xicor.com october, 2000 time power (ua-hr) dt = 13ms dt = 660ms 100khz 5mhz standby 11 a 11 a active 7.02ma 8 ma system current 1mhz 11 a 7.2ma dt = 66ms figure 4. power vs. interface speed. this ?ure shows an example of a processor that draws 7ma active and 10 a in standby. the serial memory current increases linearly as the speed increases. having the processor active for less time reduces system power, demonstrating one value of a high speed serial device. i 2 c bus speed 400mhz 12mhz 10mhz 1mhz 100khz peripheral bus memory i/o bus 25mhz 2 5 1394 usb spi 20 40 1ghz wire figure 5. serial bus speed trends. there are two kinds of serial busses, peripheral and memory. the i 2 c bus is both. as the need for performance increases, the speed of peripheral and memory busses increase.
6 of 9 an 113 application note www.xicor.com october, 2000 the microwire bus as one of the oldest serial busses, the microwire bus has been a popular and high volume solution for a long time. it supports some of the lowest cost serial memories and is fast enough for many applications. however, there are a few drawbacks. 1. the microwire interface does not support as many density options as the other interfaces, with densities topping out at 16kbits. there also have been few new products intro- duced with this bus. this limits the designer s choices in new designs. 2. the microwire requires more port pins than the i 2 c bus, so it s use can be more costly to the system designer. 3. the microwire bus is limited in speed and architecture. microwire devices limit the interface speed to 1mhz and clock data out and in on the same edge. this imposes some limitations on the design. a similar bus (spi) clocks data in and out on opposite edges of the clock and has higher speed speci?ations. so while microwire has some advantages, it will likely be one of the ?st of today s serial busses to disappear. the i 2 c bus the i 2 c bus, developed at about the same time as the microwire bus, will likely be around for some time. since it was developed as a peripheral bus, it works very well in systems that have few ports available on the host controller and must connect to a number of peripheral devices. some of the more common i 2 c devices are a/d converters, lcd displays, real time clocks and memories. in 1985 xicor introduced a 2-wire serial memory device that could operate on the i 2 c bus. xicor still leads the industry in 2-wire density, interface speed and features and has one of the widest selections of 2-wire memories with densities ranging from 128 bits to 128kbits. the original i 2 c bus speci?d 100khz maximum speed. based on industry feedback, this increased to 400khz, but likely will not increase it further. the i 2 c bus speed limit results from it s peripheral roots. potentially long i 2 c bus lengths and the activity of a number of devices on the bus (including multiple masters) increase the possibility of noise induced errors as the speed increases. this, coupled with the indeterminate loading and colli- sion detection protocols, makes i 2 c a noise sensitive interface. the i 2 c interface consists of two lines clock (scl) and data (sda). the protocol speci?s that communication begins with a start bit and ends with a stop bit. data going high to low while the clock is high de?es a start bit (figure 6) data going low to high while the clock is high de?es a stop bit. during transmission of data the sda line cannot change while the clock is high. this protocol makes it dif?ult to discriminate between a start/stop bit and data on a higher speed, noisy bus. noise on the i 2 c bus can sometimes result in corrupted data. in the i 2 c protocol, a random read of the array (figure 7) consists of two parts. first, the host writes the address where the desired read will start. then the host sends a repeated start bit followed by a current address read instruction. the host then clocks data in from the sda line. since the current address read instruction differs from a write instruction by a single bit, noise at a critical time turns a read operation into a write and clocks intended to read data into the host become clocks writing data into the device. the result can be uncontrol- lable data corruption. this doesn t happen often, but when it does it can be serious. to limit the probability of this type of error, xicor intro- duced 2-wire devices that provided input noise ?tering, schmidt triggers and input latching. to give engineers additional control over memory write operations, all new 2-wire devices include block lock features. this gives the system designer the ability to lock critical parts of the array, so unexpected and uncontrolled writes due to noise cannot damage critical system data. in order to allow a number of peripherals to connect to the same set of two wires, the i 2 c bus requires an open collector with pull-up on the sda output of any device on the bus. for multi-master systems, the scl line also needs an open collector and a pull-up. this con?uration allows one device to ?in?over another when two devices try to send data at the same time (collision).
7 of 9 an 113 application note www.xicor.com october, 2000 however, this con?uration increases system power, since there is 270 a 1 current ?wing through the pull- up resistor for the duration of a ??bit . in summary, the i 2 c bus has the advantages of needing few port pins and supporting a number of peripheral devices. however, the i 2 c bus has the disadvantages of slow speed, noise susceptibility and higher system current. the spi bus motorola created the spi port in the mid 1980 s for use with their 68hc11 and 68hc05 product families. the spi port shares similarities with the microwire port, using similar signal names and command protocols. spi clocks data in and out differently from the microwire and can be clocked at a much higher rate. xicor was the ?st company to introduce an spi serial memory (the x25c02 in 1991) and led the industry in developing higher density devices. xicor also pioneered the use of block lock tm mechanisms on spi devices to improve data integrity. in the last few years microcon- trollers, dsps, risc processors and asics all feature built-in spi ports. these developments prompted dataquest in 1996 to report spi as the fastest growing serial interface. today, as processors increase in perfor- mance, the capabilities of the spi port increase. to keep up with this trend, xicor recently introduced spi memo- ries with a 5mhz clock rate and plans future speed increases. the spi interface consists of four control lines: cs , sck, so, and si. the host controls the cs line to select the serial memory, then uses the clock and data lines to transfer data back an forth. current implementations of the spi interface are ?alf duplex? meaning that data does not go out on the so line while writing data on the si line. so it is possible to connect si and so to get a three wire interface. most spi implementations can work in a ?ull duplex?mode. that means that data clocks into the device at the same time data clocks out. this can help increase the data throughput. future spi memories will likely take advantage of this full duplex capability. the spi interface is command driven (figure 8.) to read data from the memory, the host selects the device, sends a read command, sends the address of the desired data, then clocks the data out of the device through the so pin. at the end of the transaction, the host deselects the device. there are commands to read and write the array, read (rdsr) and write (wrsr) to a status register, and set (wren) and clear (wrdi) a write enable latch. before any successful nonvolatile write to an spi device, the host must select the device, send a wren command, deselect the device, select the device again, send a write command, send the 16 bits of address (older low density devices had 8 address bits), send a multiple of 8 bits and deselect the device. any violation of this sequence terminates a write operation. also, the comple- tion of a nonvolatile write resets the write enable latch, forcing the entire sequence to be repeated for the next write operation. this makes spi memories insensitive to noise. block locking further decreases the probability of inadvertent writes due both to noise and programming glitches. spi is a high speed memory port supported by a variety of microcontrollers, dsps and asics. it is growing in popularity as host performance increases and as built in spi ports become more common. new features as well as higher speeds indicate that the spi interface will be around for quite a while. 1. assumes 100pf bus capacitance and 2.7v operation.
8 of 9 an 113 application note www.xicor.com october, 2000 scl sda start stop scl sda data stable data change data stable figure 6. i 2 c start, stop and data bits 0 slave address byte address a c k a c k s t a r t s t o p slave address data a c k 1 s t a r t sda bus signals from the slave signals from the master figure 7. i 2 c random read - this ?ure shows a random read of one byte. 7654321 0 11 3 2 1 0 cs sck si so 54 command address data (1 byte) (2 byte) figure 8. spi read command
9 of 9 an 113 application note www.xicor.com october, 2000 conclusion industry-wide, there is a trend to serial interfaces and away from parallel, as demonstrated by several new industry standards. the need for low power, small size and lower cost fuels this conversion and there is no sign that the trend will change in the near future. in order to provide a communication medium to the serial memory, there are several types of interfaces. the discussion here focused on 2-wire and spi solutions. the value of each lies in the design trade-off between how they connect to the host and how fast each transfers data. in recent years, consumers have demanded more porta- bility, performance and customization from the products they buy. these needs fueled decreases in package size and power and increases in memory density and speed. with state of the art speed and packaging, xicor 2-wire and spi serial memories provide designers and consumers with the right solutions for today and for the future.
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